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A silicon structure for electrical characterization of nanoscale elements

P.J.A.Sazio1, J.Berg2, P.See1, C.J.B.Ford1, P.Lundgren2, N.C.Greenham1, D.S.Ginger1, S.Bengtsson2, and S.N.Chin1

1. University of Cambridge, Cavendish Laboratory, Madingley Road, Cambridge CB3 0HE, UK
2. Chalmers University of Technology, Department of Microelectronics ED, SE-412 96 Göteborg, Sweden


The problem of mass manufacturing electrode structures suitable for contacting nanoscale elements lies primarily in the difficulty of fabricating a nanometre-scale gap between two electrodes in a well controlled, highly parallel manner. In ULSI circuit production, the gate and substrate in MOSFETs are routinely fabricated with a precise vertical spacing of 3 nm between them. In this work, we have investigated a number of highly parallel methods for the generation of nanogaps, including reconfiguration of the ubiquitous MOS device structure. The silicon dioxide layer that provides vertical separation and electrical insulation between two regions of silicon (the crystalline substrate and the poly-crystalline gate) gives a leakage current of 1 nA μm-2 at 1 V for an oxide thickness of 2 nm [1]. This will enable objects the size of single molecules that are held across this layer to be detected electrically if they provide currents on the nanoampere scale, assuming a parasitic area for leakage between gate and substrate of order 1 μm2. In the future this kind of device has the potential to provide a bolt-on technology for the fabrication of ULSI circuits in which conventional CMOS devices are directly hybridised with functional nanoscale elements.

Materials Research Society Symposium Proceedings (2001) pp.B2.3.1-B2.3.6 673E (Spring)

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Copyright University of Southampton 2006