Better on-wafer testing promises to bring silicon photonics nearer to mass manufacturing
University of Southampton researchers have presented unique erasable grating technology at the SPIE Photonics West show; companies can gain access via the EPSRC-funded Future Photonics Hub.
Erasable grating couplers that can provide more detailed information in automated testing could be set to enable more effective large-scale manufacturing of silicon photonic devices. That’s according to University of Southampton researchers who will present the latest results of their work at the SPIE Photonics West conference, which runs until February 2 2017 in San Francisco. Furthermore, companies interested in this technology can get involved via the Southampton-led Future Photonics Hub, the UK’s centre for linking academic expertise with industry to establish a pathway to manufacture for next-generation photonics technologies. “As far as I’m aware, no-one else has this erasable grating capability,” stresses Professor Graham Reed, Head of the Silicon Photonics Group at Southampton’s world-renowned Optoelectronics Research Centre.
Manipulating light using ubiquitous silicon, rather than more expensive conventionally-used materials, holds the prospect of bringing photonics to mass markets, and making millions of devices. Silicon photonics is already used in fibre-optic communication, with near-term opportunities in helping move more information around data centres, like those run by Facebook and Google. Production volumes will increase further with fibre-to-the-home networks, and even connections within homes, as well as spectroscopic sensing including detecting explosives, drugs and pollution. Sensing also offers large volume opportunities in devices for medical and biological testing. Emulating the low costs that silicon electronic devices achieve requires photonic devices to be tested directly on silicon wafers.
“In an electronic circuit a connection will give you a signal without detracting from performance,” Professor Reed says. “You can’t really do that in optical circuits. You have to take light out of the chip to test it, which is very difficult.”
One option is making a permanent grating on the surfaces of silicon photonics chips. However that grating always lets light in or out, potentially affecting the chip’s final performance. Consequently, only the main input and output gratings are used for wafer-scale automated testing. “That means you can only test the whole chip,” Professor Reed explains.
“We could never test a critical component, for example one that’s prone to manufacturing tolerance-based variations because you can’t access that isolated component. If the circuit doesn’t work, you have no idea why.”
Together with his research group, Professor Reed has developed gratings that can be fabricated using ion implantation and then later erased by laser annealing:
“In other words, once we’ve done the testing, we can shine a laser onto that grating, and make it disappear. We can put as many gratings as we like into the circuit, and therefore test any component.” He explains that many erasable gratings might be used while prototype silicon photonic devices are being developed to study how they’re performing. The final products may however retain only those near to critical components.
The Southampton scientists first reported the approach in 20141 but will describe their latest efforts in shrinking the gratings at the world’s largest multidisciplinary event for photonics, the forthcoming SPIE Photonics West 2017.
“These additional coupling points take up space in your circuit, adding cost,” Professor Reed says. “We’re targeting devices that are 100 µm long or less.” The team has also established another technology, currently at a far earlier stage of development, which has no impact on the size of the circuits. Professor Reed will discuss erasable gratings during an invited talk at the Smart Photonic and Optoelectronic Integrated Circuits XIX conference2 (Wednesday 1 February 2017, 8:30am), while his colleague Dr Milan Milosevic will present related work at the Silicon Photonics XII conference 3 (Wednesday 1 February 2017, 2:10pm). Reed is also co-chair of the OPTO symposium at Photonics West 2017, which constitutes about a third of the overall meeting and includes more than 30 separate conferences.
The Silicon Photonics Group is studying other areas of automation for volume silicon photonics manufacturing and feeding the knowledge into the Future Photonics Hub for industrial applications. This includes the passive alignment of fibres with silicon waveguides and automated positioning for integrating other materials onto silicon chips. The materials being explored include germanium sensors, compound semiconductor light sources, non-linear polymer and silicon-germanium modulators, and silicon nitride layers that enable stacks containing multiple photonic devices.
If you would like to find out more, visit the Future Photonics Hub at Photonics West at booth 5037, Hall D (North Hall), part of the UK Pavilion, where will be able to talk with members of the team about opportunities for joint projects. You can book an appointment to meet with Dr John Lincoln, Industrial Liaison Manager at: http://www.doodle.com/photonicshub.
Download a full schedule of all the papers and posters featuring Hub investigators at the conference at: http://photonicshubuk.org/wp-content/uploads/sites/93/2016/08/In-the-conference-Hub.pdf